1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a method for forming epitaxial Co self-align suicide for a semiconductor device suitable for high-integrated semiconductor devices.
2. Description of the Background Art
As semiconductor devices become miniaturized up to 0.18 to 0.13.mu., plate resistance of a microgate is increased. In order to settle such a problem, Co-silicide will be widely applied to gates having size under 0.18.mu., since it has low resistance in micropatterns compared to Ti-silicide which is currently used.
A conventional method for fabricating a semiconductor device using Co-silicide having low resistance will be described with reference to the accompanying drawings.
As shown in FIGS. 1A and 1B, a gate electrode 3 is formed on a silicon substrate 1 wherein an active domain 1a and an isolated domain 1b are defined, and an insulating film 4 is formed on the silicon substrate 1 including the gate electrode 3. The insulating film 4 is formed of a silicon oxide film by a chemical vapor deposition method (CVD). A reference numeral 2 is a field insulator film.
In FIG. 1C, an anisotropic etching process is applied to the insulating film 4 without a mask, for thereby forming a sidewall spacer 5 at each side of the gate electrode 3, and an impurity area 6 is formed by which an ion implantation is applied to an externally exposed part of the silicon substrate 1 by using the gate electrode 3 and the sidewall spacer 5 as a mask. When the silicon substrate 1 is p-type, an n-type impurity such as As, P is implanted into the impurity area 6, for thereby fabricating an NMOS transistor. Whereas, when the silicon substrate 1 is n-type, a PMOS transistor is fabricated by an ion implantion of a p-type impurity such as B, BF.sub.3 into the area 6.
As shown in FIGS. 1D and 1E, a Co layer 7 is formed on the entire surface of the silicon substrate 1, including the gate electrode 3 and the sidewall spacer 5 by CVD, and a Co self-align silicide layer 8 is formed in the gate electrode 3 and the impurity area 6 by annealing the Co layer. Here, a part of the Co layer 7 which is formed on the sidewall spacer 5 is removed by a wet etching method.
However, the conventional method for forming the Co-silicide for the semiconductor device has several problems.
When applying the annealing process after depositing the Co layer, cobalt and silicon radically react on each other and thus silicon in the gate electrode and the impurity area is excessively consumed, and the Co-silicide layer is excessively formed. Accordingly, it is difficult to form a shallow junction required for scaling down the semiconductor device in order to increase the integration thereof.
In addition, there is a limit to decrease resistance due to limit of specific resistance of multi-crystalline Co-silicide, and since thickness of the Co-silicide layer is not uniform, the uniformity of contact resistance and plate resistance thereof may not be obtained.
To solve such problem, the silicon substrate is put in a wet chemical, for thereby having many porosities at a surface thereof, and then cobalt is deposited thereon and the annealing process is applied. Although epitaxial Co-silicide may be formed according to the above method, an uneven silicide layer is formed due to the composition of the chemical because the chemical applied to the substrate is a hot solution containing hydrogen peroxide.